Apparatuses including cross point memory arrays and biasing schemes

摘要

Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

主权项

1. An apparatus, comprising:
a three-dimensional array of cross-point memory cells, including:
a first set of address lines extending in a first direction;a second set of address lines extending in a second direction transverse to the first direction, wherein pairs of adjacent intersections of the first set and the second set define at least one memory cell between them, and wherein:
a first plurality of memory cells is located between a first address line of the first set of address lines and the second set of address lines in a first plane; anda second plurality of memory cells is located between the second set of address lines and a second address line of the first set of address lines in a second plane; andcontrol circuitry configured to bias the first set of address lines and the second set of address lines according to a bias scheme that causes at least one memory cell of the first plurality of memory cells in the first plane and at least one memory cell of the second plurality of memory cells in the second plane to have a same data value accessed within a single clock cycle while at least one other memory cell of the first plurality of memory cells in the first plane and at least one other memory cell of the second plurality of memory cells in the second plane are not accessed within the single clock cycle.