| 摘要 |
A memory device having an addressing unit for addressing different values as addresses for input/output of data for each clock input during one cycle, and a memory inputting data at different designated addresses and cyclically outputting stored data. The memory device provides the operation of a shift register which is capable of determining the number of stages in accordance with the content of the addressing. By employing a memory which effects read-modify-write operations and by delivering input data obtained by the feedback of output data to this memory, the memory device can repeatedly output the same data. The memory device has a switch circuit operative in a first position for connecting an output of the memory to an input of the memory and in a second position for connecting the input of the memory to an external data source.
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