Apparatus for generating test pattern for sequential logic circuit of integrated circuit and method thereof,申请号EP19920106403-传众专利搜索

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发明名称	Apparatus for generating test pattern for sequential logic circuit of integrated circuit and method thereof
摘要
申请公布号	EP0509440(B1)	申请公布日期	1997.07.09
申请号	EP19920106403	申请日期	1992.04.14
申请人	MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.	发明人	TAKEOKA, SADAMI;MOTOHARA, AKIRA
分类号	G01R31/3183;G01R31/28;G01R31/3185;G06F11/22;(IPC1-7):G06F11/26	主分类号	G01R31/3183
代理机构		代理人
主权项
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