发明名称 |
Dynamically reconfigurable signal processing circuit, pattern recognition apparatus, and image processing apparatus |
摘要 |
A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement information read from a circuit arrangement information storage unit. Hierarchical parallel processing is realized with small-scale circuit configuration. Further, detection of a predetermined feature and integration of the detection results can be efficiently performed.
|
申请公布号 |
US7088860(B2) |
申请公布日期 |
2006.08.08 |
申请号 |
US20020105309 |
申请日期 |
2002.03.26 |
申请人 |
CANON KABUSHIKI KAISHA |
发明人 |
MATSUGU MASAKAZU;MORI KATSUHIKO;NOMURA OSAMU |
分类号 |
G06K9/00;G06K9/46;G06K9/66 |
主分类号 |
G06K9/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|