发明名称 FAILURE SPOT ESTIMATION SYSTEM OF MULTIPLE FAILURE IN LOGIC CIRCUIT, FAILURE SPOT ESTIMATION METHOD, AND FAILURE SPOT ESTIMATION PROGRAM
摘要 PROBLEM TO BE SOLVED: To reduce the number of combinations of failure candidates, and to shorten an estimation processing time, while estimating a failure spot accurately, even when being influenced mutually by wrong propagation routes from a plurality of failures. SOLUTION: This system is equipped with a single failure assumption diagnosis means 22 for assuming a single failure, and storing a failure candidate, a failure kind, and an error observation node reached by an error from the failure candidate and detected; a candidate classification means 23 classified by each error observation node for grouping failure candidates propagating each error in each observation node by using the failure candidates and each error observation node, and storing the result as each failure candidate group; an included failure candidate group selection means 24 for deleting an included failure candidate group, when route information of some failure candidate group includes route information of another failure candidate group; a superposition means 25 between patterns for extracting common failure candidates in the failure candidate groups calculated by means of a plurality of patterns, and forming a new failure candidate group; and a multiple failure simulation collation means 26 for outputting a combination of failure candidate groups having strong failure possibility. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008089549(A) 申请公布日期 2008.04.17
申请号 JP20060274031 申请日期 2006.10.05
申请人 NEC ELECTRONICS CORP 发明人 FUNATSU YUKINAGA
分类号 G01R31/28 主分类号 G01R31/28
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