发明名称 PARALLEL PROCESSING OF PLATFORM LEVEL CHANGES DURING SYSTEM QUIESCE
摘要 Various embodiments described herein provide one or more of systems, methods, and software/firmware that provide increased efficiency in implementing configuration changes during system quiesce time. Some embodiments may separate a quiesce data buffer into small slices wherein each slice includes configuration change data or instructions. These slices may be individually distributed by a system bootstrap processor, or other processor, to other processors or logical processors of a multi-core processor in the system. In some such embodiments, the system bootstrap processor and application processors may change system configuration in parallel while a system is in a quiesce state so as to minimize time spent in the quiesce state. Furthermore, typical system configuration change become local operations, such as local hardware register modifications, which suffer much less transaction delay than remote hardware register accesses as has been previously performed. These embodiments, and others, are described in greater detail herein.
申请公布号 US2009077553(A1) 申请公布日期 2009.03.19
申请号 US20070854953 申请日期 2007.09.13
申请人 TANG JIAN;LI YUFU 发明人 TANG JIAN;LI YUFU
分类号 G06F9/46 主分类号 G06F9/46
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