发明名称 Error protection for memory devices
摘要 Subject matter disclosed herein relates to methods and/or apparatuses, such as an apparatus that includes first and second groups of memory cells. The first group of memory cells stores multiple digits of program data per memory cell. The second group of memory cells stores a parity symbol per memory cell. Other apparatuses and/or methods are disclosed.
申请公布号 US9361181(B2) 申请公布日期 2016.06.07
申请号 US201213421578 申请日期 2012.03.15
申请人 Micron Technology, Inc. 发明人 Laurent Christophe;Amato Paolo;Fackenthal Richard
分类号 G11C29/00;G11C11/34;G11C16/04;G06F11/10;G11C11/56;G11C16/10;H03M13/19;G11C29/04 主分类号 G11C29/00
代理机构 Brooks, Cameron & Huebsch, PLLC 代理人 Brooks, Cameron & Huebsch, PLLC
主权项 1. A method comprising: storing codeword data, including program data and associated parity data, in a group of multi-level memory cells, wherein the storing the codeword data comprises: storing only a single bit of parity data per multi-level memory cell for storing the parity data, wherein no program data is stored in multi-level memory cells storing the associated parity data, wherein none of the multi-level memory cells of the group storing program data stores any parity data, and wherein each of the multi-level memory cells of the group storing program data stores more than one bit of program data;wherein the parity data are capable of being changed more than once without erasing corresponding memory cells of the group of memory cells; changing the program data stored in the multi-level memory cells of the group storing program data; and responsive to changing the program data, reprogramming the multi-level memory cells of the group storing the associated parity data prior to performing an erase operation on the multi-level memory cells storing the associated parity data.
地址 Boise ID US