Compiler directed cache coherence for many caches generated from high-level language source code

摘要

Approaches for generating and operating an electronic system. High-level language (HLL) source code is compiled into equivalent intermediate language program code. The compilation determines a plurality of caches for storing data referenced by the HLL source. Flush instructions are inserted in the intermediate language program. Each flush instruction references one of caches and is inserted in the intermediate language program immediately following an instruction that is last to write to that cache. The intermediate language program is translated into a hardware description that specifies the plurality of caches, circuits for processing data in the caches, and for each of the caches a flush interface that initiates writing data from the cache to a main memory in response to a flush signal. The timing of the respective flush signal is determined based on placement of one of the one or more flush instructions in the intermediate language program.

主权项

1. A method for generating an electronic system specification from high-level language (HLL) source code, comprising:
compiling by a computing arrangement, at least part of the HLL source code into an intermediate language program equivalent to the part of the HLL source code, wherein the compiling includes: determining from the HLL source code a plurality of caches for storing data referenced by the HLL source; and inserting one or more flush instructions in the intermediate language program, wherein each flush instruction references one of caches and is inserted in the intermediate language program immediately following an instruction that is last to write to the one of the caches; and translating the intermediate language program into a hardware description that specifies the plurality of caches, circuits for processing data in the caches, and for each of the caches a flush interface that initiates writing data from the cache to a memory structure in response to a respective flush signal, wherein timing of the respective flush signal as specified in the hardware description is determined based on placement of one of the one or more flush instructions in the intermediate language program.