| 摘要 |
A phase-frequency detector (PFD) having substantially linear phase error gain within a predetermined phase error range centered about zero phase error when used in a delta sigma phase-locked loop (PLL). The output signals (e.g., charge pump control signals), which are also used to reset the input circuitry, are fed back with asymmetrical signal delays, thereby causing one of the output signals to remain in an asserted state for a substantially constant time duration at least during when a difference between the reference and feedback signal phases is within a predetermined phase difference range centered about zero phase difference.
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