Fast parity generator using complement pass-transistor logic

摘要

The present invention discloses a fast parity bit generator using 4-bit XOR cells implemented using complement pass-transistor logic. For 22n inputs, where n is an arbitrary positive integer, the parity bit is generated in n stages using only <IMAGE> 4-bit XOR cells. For 22n+1 inputs, where n is an arbitrary positive integer, the parity bit is generated using <IMAGE> 4-bit XOR cells disposed in n rows and one 2-bit XOR cell disposed in the last row. The speed of operation of the XOR cells is further enhanced by using NMOS transistor logic within the XOR cells.