发明名称 |
Debugging system using virtual storage means, a normal bus cycle and a debugging bus cycle |
摘要 |
A debugging system is adapted to perform debugging by employing a virtual address in a computer system which includes a microprocessor incorporating a virtual storage function and a function for outputting a normal bus cycle corresponding to a real address in a normal operation and a function for outputting a debugging bus cycle corresponding to a virtual address. The microprocessor outputs a signal indicative of a kind of access and a signal indicative of an outputting state of a virtual address during outputting of the virtual address in the debugging bus cycle. A memory device is connected to the microprocessor through an address bus and a data bus. The debugging system includes a bus monitoring means for monitoring output of the processor, the output from bus cycles and transfer data. The bus monitoring means includes a debugging means for performing the debugging process associated with the virtual address.
|
申请公布号 |
US5608867(A) |
申请公布日期 |
1997.03.04 |
申请号 |
US19940223654 |
申请日期 |
1994.04.05 |
申请人 |
NEC CORPORATION |
发明人 |
ISHIHARA, TOSHINORI |
分类号 |
G06F11/28;G06F11/36;(IPC1-7):G06F11/30 |
主分类号 |
G06F11/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|