发明名称 |
INNER CLOCK SYNCHRONIZING METHOD/CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To immediately synchronize an inner clock by means of the sampling of a phase comparison result by using the edge of a source oscillation clock. SOLUTION: A clock comparison means 11 compares the inner clock SCK 2 generated by frequency-dividing the source oscillation clock Xin by a clock generation means 10 with an inputted reference clock SCK1. A comparison result signal COMP which the clock comparison means 11 outputs is held in a comparison result holding means 12 in synchronizing with the source oscillation clock. The input of the source oscillation clock to a clock generation moans 10 is opened/closed by a clock opening/closing means 13 controlled by a comparison result signal/COMPD held by the comparison result holding means 12. |
申请公布号 |
JPH11205293(A) |
申请公布日期 |
1999.07.30 |
申请号 |
JP19980007941 |
申请日期 |
1998.01.19 |
申请人 |
MITSUBISHI ELECTRIC CORP |
发明人 |
YAMAZAKI TAKASHI |
分类号 |
G06F15/16;G06F1/10;G06F1/12;G06F15/177;H03L7/00;H03L7/085;H03L7/099;H04L7/00;H04L7/033 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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