发明名称 Method for verifying a circuit design by assigning numerical values to inputs of the circuit design
摘要 A method for verifying a circuit design includes a step of assigning numerical values 1/a<SUB>i </SUB>to input ports of the circuit design according to a function a<SUB>i+1</SUB>=(a<SUB>i</SUB>-1)<SUP>2</SUP>+1, wherein i represents the number of the input port and the numerical value a<SUB>1 </SUB>is not equal to 2 or 1. Preferably, a<SUB>1 </SUB>is equal to or larger than 3, and is a positive integer. Particularly, the numerical value represents l's probability. In addition, the present method further includes a step of calculating an output value at an output port of the circuit design based on the numerical values assigned to the input port, and calculating the output value is performed from the input port to the output port at a Boolean gate level.
申请公布号 US7302655(B2) 申请公布日期 2007.11.27
申请号 US20050152472 申请日期 2005.06.14
申请人 NATIONAL TSING HUA UNIVERSITY 发明人 WANG CHUN-YAO;HSIEH JAN-AN;WU SHIH-CHIEH
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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