The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
申请公布号
EP3031047(A2)
申请公布日期
2016.06.15
申请号
EP20140815431
申请日期
2014.08.06
申请人
MOLONEY, DAVID;RICHMOND, RICHARD;DONOHOE, DAVID;BARRY, BRENDAN;BRICK, CORMAC;VESA, OVIDIU ANDREI
发明人
MOLONEY, DAVID;RICHMOND, RICHARD;DONOHOE, DAVID;BARRY, BRENDAN;BRICK, CORMAC;VESA, OVIDIU ANDREI