Sample hold circuit, A/D converter, calibration method of the sample hold circuit, and circuit

摘要

There is provided a pipelined A/D converter in which plural stages Stage 1 to Stage N each including an MDAC (i.e., Multiplying DA Converter) are connected. The pipelined A/D converter is configured with a Gain-AMP (12) included in the MDAC for the SPM, MOS transistors (Mx1) and (Mx2) as a differential pair having output ends connected to a sampling capacitor CsI on a subsequent stage, MOS transistors (My1) and (My2) as a load unit connected to the differential pair, a current source (I3) configured to supply a current to the MOS transistors (Mx1) and (Mx2) as the differential pair, and current sources (I1) and (I2) configured to adjust the current flown across the MOS transistors (My1) and (My2) as the load unit.

主权项

1. A sample hold circuit, comprising:
a sampling capacitor; a first amplifier having an input end to which the sampling capacitor is connected; and a second amplifier connected to the first amplifier, wherein the second amplifier comprises: a differential pair; a load unit connected to the differential pair; and a variable current unit configured to supply a current to at least one of the differential pair or the load unit, and wherein in a holding phase, the second amplifier is configured to monitor a voltage at a summing point that is a connection point of the sampling capacitor at the input end of the first amplifier.