Semiconductor memory device including flag cells

摘要

A semiconductor memory device includes a plurality of memory cells arranged in a row direction and a column direction, a plurality of word lines each connected to memory cells in a row among the memory cells, and a majority of bit lines each connected to memory cells in a column among the memory cells. One or more memory cells are distributed as flag cells among memory cells connected to each word line, and flag cells connected to a first word line and flag cells connected to a second word line that is disposed adjacent to the first word line among the word lines are connected to first and second bit lines, respectively.

主权项

1. A semiconductor memory device comprising: a plurality of memory cells arranged in a row direction and a column direction; a plurality of word lines, each of the plurality of word lines coupled to memory cells in a row among the plurality of memory cells; N input/output lines, where N is a natural number greater than 1: and a plurality of bit lines including a first group of bit lines and a second group of bit lines, each of the plurality of bit lines coupled to memory cells in a column among the plurality of memory cells, each of the first group of bit lines and the second group of bit lines including N bit lines connected to the N input/output lines, respectively, wherein memory cells coupled to each of the plurality of word lines include main cells and flag cells storing flag data for managing the main cells, first M flag cells coupled to a first word line among the plurality of word lines are coupled to first M bit lines among the N bit lines included in the first group of bit lines, the first M bit lines connected to first M input/output lines among the N input/output lines, respectively, where M is a natural number less than N second M flag cells coupled to the first word line are coupled to second M bit lines among the N bit lines included in the second group of bit lines, the second M bit lines connected to the first M input/output lines, respectively, third M flag cells coupled to a second word line adjacent to the first word line are coupled to third M bit lines among the N bit lines included in the first group of bit lines, the third M bit lines connected to second M input/output lines different from the first M input/output lines among the N input/output lines, respectively lines, and fourth M flag cells coupled to the second word line are coupled to fourth M bit lines among the N bit lines included in the second group of bit lines, the fourth M bit lines connected to the second M input/output lines, respectively, wherein flag cells of each word line are distributed such that K (K is a natural number greater than 2) adjacent flag cells are distributed between main cells.