| 摘要 |
<p>According to this invention, a well region (17) is formed on a semiconductor substrate (11). An n<+>-type first semiconductor region (12) is formed in the well region (17), and an input pad (18) for receiving an external signal is connected near the first semiconductor region (12). This input pad (18) is connected to an input circuit (IN) of an integrated circuit constituted by an inverter circuit and to an external terminal (16) for receiving an external signal. N<+>-type second semiconductor regions (13, 14) are formed in the well region (17) located on both the sides of the first semiconductor region (12). A ground potential (Vss) is applied to these second semiconductor regions (13, 14). A p<+>-type third semiconductor region (15) is formed around these second semiconductor regions (13, 14) in the well region (17). The ground potential (Vss) is applied to the third semiconductor region (15). Therefore, a parallel circuit formed by a parasitic transistor (19) and a parasitic diode (10) is formed between the input pad (18) and the ground potential (Vss). The parasitic transistor (19) is turned on upon electrostatic discharge, and the parasitic diode (10) is turned on when a negative potential (VIL) for test is applied to the input pad (18), thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate (11). <IMAGE></p> |
