发明名称 TEST MODE SETTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent a method for setting a test mode outputting a ROM code from being detected by a third party by providing a test mode setting circuit with first and second detection means detecting whether the pulse width of input signal from an external terminal is contained in a range preliminarily set, and first and second storing means storing it. SOLUTION: A signal to be applied to an external terminal 101 is input to an AND gate 102. To a pulse width detection circuit 103 an output signal of the AND gate 102 is input, and only when the high level width W1 of the signal satisfies a relation of D1<=W1 (D1+Δ1) a high level pulse of 1 shot is output therefrom. A flip-flop circuit of a NOR stages 105, 106 and an inverter 107 is high when a signal 104 is high pulse, while low when a reset signal is high pulse. Similarly, to a pulse width detection circuit 114 an output signal of an AND gate 113 is input, and only when the high level width W2 of the signal satisfies a relation of 2<=W2<(D2+Δ2) a high pulse of 1 shot is output therefrom. This is used as a test mode signal 116 accordingly.
申请公布号 JPH10142300(A) 申请公布日期 1998.05.29
申请号 JP19960300304 申请日期 1996.11.12
申请人 NEC CORP 发明人 HASEGAWA YASUYUKI
分类号 G01R31/28;G01R31/3185;G06F12/14;G06F21/24;H01L21/822;H01L27/04;(IPC1-7):G01R31/318 主分类号 G01R31/28
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