发明名称 Handling exceptions occurring during processing of vector instructions
摘要 The data processing apparatus and method comprises an instruction decoder for decoding a vector instruction representing a sequence of data processing operations, and an execution unit comprising a plurality of pipelined stages for executing said sequence of data processing operations. The execution unit includes exception determination logic for determining, as each instruction enters a predetermined pipelined stage, whether that data processing operation is an exceptional operation matching predetermined exception criteria, the execution unit being arranged to halt processing of said exceptional operation. Further, an exception register is provided for storing exception attributes relating to said exceptional operation, said exception attributes indicating which data processing operation in said sequence has been determined to be said exceptional operation. This enables the exception attributes stored in the exception register to be provided to an exception processing tool for use in handling said exceptional operation. By this approach, it is possible for an exception processing tool to be used to handle the specific exceptional operation that has given rise to the exception condition, rather than providing the entire vector instruction for handling by the exception processing tool. Further, since the whole vector instruction does not need to be handled by an exception processing tool in the event of an exception being detected, it is possible for the registers holding data values associated with a particular data processing operation in the sequence to be released for use by subsequent instructions as soon as execution of that data processing operation has completed, rather than having to ensure that those registers are "locked" until the entire vector instruction has completed.
申请公布号 GB9908541(D0) 申请公布日期 1999.06.09
申请号 GB19990008541 申请日期 1999.04.14
申请人 ARM LIMITED 发明人
分类号 G06F17/16;G06F9/38 主分类号 G06F17/16
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