发明名称 VERIFICATION SEQUENCE DETERMINING PROGRAM, VERIFICATION SEQUENCE DETERMINING METHOD, AND VERIFICATION SEQUENCE DETERMINING DEVICE
摘要 PROBLEM TO BE SOLVED: To accurately determine the sequence of tests for verification.SOLUTION: A verification sequence determining program causes a computer to execute processing to calculate for each test a priority level representing the relative priority of logic verification on the basis of predictive information predicting for each module involved in logic verification the probability of trouble occurrence and the comprehensiveness of tests to a module when a test for logic verification is performed. Also, the verification sequence determining program causes the computer to execute processing to output, on the basis of a priority level calculated for each test, the sequence of verification to be conducted on tests.SELECTED DRAWING: Figure 2
申请公布号 JP2016091062(A) 申请公布日期 2016.05.23
申请号 JP20140220815 申请日期 2014.10.29
申请人 FUJITSU LTD 发明人 PARISI MATTHEW;KANAZAWA YUJI
分类号 G06F17/50 主分类号 G06F17/50
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