Integrated oxide recess and floating gate fin trimming

摘要

Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.

主权项

1. A method of forming a floating gate, the method comprising:
transferring a patterned substrate into a substrate processing mainframe, wherein the patterned substrate comprises two polysilicon floating gates separated by shallow trench isolation silicon oxide gapfill dielectric, wherein the two polysilicon floating gates each have vertical sidewalls; transferring the patterned substrate into a first substrate processing chamber mounted on the substrate processing mainframe; flowing a fluorine-containing precursor and a hydrogen-containing precursor into a first remote plasma region within the first substrate processing chamber while striking a plasma to form first plasma effluents from a combination of the fluorine-containing precursor and the hydrogen-containing precursor; flowing the first plasma effluents into a first substrate processing region within the first substrate processing chamber; wherein the first substrate processing region houses the patterned substrate; reacting the first plasma effluents with the shallow trench isolation silicon oxide gapfill dielectric to form solid residue and sublimating the solid residue; transferring the patterned substrate from the first substrate processing chamber to a second substrate processing chamber mounted on the substrate processing mainframe; flowing a fluorine-containing precursor into a second remote plasma region within the second substrate processing chamber while striking a plasma to form second plasma effluents and flowing the second plasma effluents through a showerhead into a second substrate processing region housing the patterned substrate within the second substrate processing chamber; isotropically etching the two polysilicon floating gates to thin their width and form sidewalls which are again vertical by reacting the second plasma effluents with the two polysilicon floating gates; and removing the patterned substrate from the substrate processing mainframe, wherein the patterned substrate is not exposed to atmosphere between transferring the patterned substrate into the substrate processing mainframe and removing the patterned substrate from the substrate processing mainframe.