发明名称 |
5v tolerant I/O circuit |
摘要 |
An integrated circuit has an I/O circuit that is connected to an I/O PAD. The I/O PAD may have greater voltage than the VDD associated with the integrated circuit so there is provided a switching circuit that is connected between the VDD and the I/O PAD. An output circuit is also provided that comprises n-channel transistors connected between the PAD and the ground. There is a cascode arrangement of p-channel transistors connected between the I/O PAD and VDD.
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申请公布号 |
US5852375(A) |
申请公布日期 |
1998.12.22 |
申请号 |
US19970797565 |
申请日期 |
1997.02.07 |
申请人 |
SILICON SYSTEMS RESEARCH LIMITED |
发明人 |
BYRNE, TIMOTHY GERARD;MORLEY, BRIAN T. |
分类号 |
H03K19/003;(IPC1-7):H03K3/00;H02H3/20 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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