发明名称 Adaptive hierarchical cache policy in a microprocessor
摘要 A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.
申请公布号 US9378148(B2) 申请公布日期 2016.06.28
申请号 US201313843315 申请日期 2013.03.15
申请人 Intel Corporation 发明人 Novakovsky Larisa;Nuzman Joseph;Gendler Alexander
分类号 G06F12/0891;G06F12/08 主分类号 G06F12/0891
代理机构 Trop, Pruner & Hu, P.C. 代理人 Trop, Pruner & Hu, P.C.
主权项 1. A processor comprising: a first storage to store a cache ratio indicator indicative of a ratio of a capacity of a second cache to a capacity of a core cache; a processing core including the core cache; the second cache; and a cache controller, including: a core eviction unit to respond to an eviction of a clean and valid cache line from the core cache by performance of an operation selected, based on a value of the cache ratio indicator, from: an inclusive eviction operation comprising: to silently drop the clean and valid cache line from the core cache; anda non-inclusive eviction operation comprising: to update the second cache to include the clean and valid cache line;a state unit to respond to a core cache miss of a targeted line, valid and modified line in the second cache, by performance of an operation selected, based on the value of the cache ratio indicator, from:a first inclusive modified operation comprising: allocation of a core cache line to store the targeted line in an exclusive state and fill the core cache line from the valid and modified line in the second cache; anda first non-inclusive modified operation comprising: allocation of a core cache line to store the targeted line in a modified state, forward the core cache line in the second cache to the core cache, and invalidate the valid and modified line in the second cache.
地址 Santa Clara CA US