METHOD OF FABRICATING MULTI-WAFER IMAGE SENSOR

摘要

A method of fabricating an image system includes forming a first wafer that includes a first semiconductor substrate and a first interconnect layer. A pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate. Additionally, a second wafer is formed that includes a second semiconductor substrate and a second interconnect layer. A second insulation-filled trench is formed in a second semiconductor substrate, and the first wafer is bonded to the second wafer. A third interconnect layer of a third wafer is bonded to the second wafer. At least one deep via cavity is formed through the first and second interconnect layers and through the first and second insulation-filled trenches. The at least one deep via cavity is filled with a conductive material to form a deep via.

主权项

1. A method of fabricating an image system, the method comprising:
forming a first wafer that includes a first semiconductor substrate and a first interconnect layer, wherein a pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate, and wherein an insulating material in the first insulation-filled trench is planarized prior to forming the first interconnect layer; forming a second wafer that includes a second semiconductor substrate and a second interconnect layer, wherein a second insulation-filled trench is formed in a second semiconductor substrate; bonding the first wafer to the second wafer, wherein the first and second interconnect layers are positioned between the first and second semiconductor layers; bonding a third interconnect layer of a third wafer to the second wafer; forming at least one deep via cavity through the first and second interconnect layers and through the first and second insulation-filled trenches, wherein the at least one deep via cavity extends to a conductor within the third interconnect layer; and filling the at least one deep via cavity with a conductive material to form a deep via.