发明名称 Distributed voltage network circuits employing voltage averaging, and related systems and methods
摘要 Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node.
申请公布号 US9494957(B2) 申请公布日期 2016.11.15
申请号 US201414482456 申请日期 2014.09.10
申请人 QUALCOMM Incorporated 发明人 Price Burt Lee;Kolla Yeshwant Nagaraj;Shah Dhaval Rajeshbhai
分类号 G01R1/30;G05F1/46;H01L21/66;G01R19/00;G01R31/30 主分类号 G01R1/30
代理机构 Withrow & Terranova, PLLC 代理人 Withrow & Terranova, PLLC
主权项 1. A distributed voltage network circuit, comprising: a voltage distribution source component comprising a plurality of source nodes; a distributed load circuit comprising a plurality of voltage load nodes; a distributed source distribution network, comprising: a plurality of resistive interconnects interconnecting each source node among the plurality of source nodes to a corresponding voltage load node among the plurality of voltage load nodes; anda plurality of voltage tap nodes, wherein each voltage tap node corresponds to a voltage load node among the plurality of voltage load nodes; and a voltage averaging circuit, comprising: a plurality of resistive elements, each resistive element among the plurality of resistive elements comprising: an input node coupled to a corresponding voltage tap node among the plurality of voltage tap nodes; andan output node; anda voltage output node coupled to the output node of each resistive element among the plurality of resistive elements, the voltage output node configured to provide an average voltage of the distributed load circuit.
地址 San Diego CA US