发明名称 METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To remove a useless test pattern at the time of selecting test pattern for executing an IDDQ test. SOLUTION: A test pattern is read out (S1), logical simulation is executed (S2), IDDQ fault detection for checking whether a fault can be newly detected in a test pattern step or not, is checked (S3), and whether the IDDQ fault detection satisfies a pattern selection reference or not, is checked (S4). When new fault detection satisfying the pattern selection reference exists, the pattern is selected (S6). Then, a fault detection table in each step of the selected test pattern is checked, whether a set of detected faults in a newly selected test pattern step includes a set of faults detected only by the selected test pattern or not, is checked, and at the time of YES, the fault set is deleted from a test pattern selection list to optimize the list.
申请公布号 JPH09212383(A) 申请公布日期 1997.08.15
申请号 JP19960014206 申请日期 1996.01.30
申请人 TOSHIBA CORP 发明人 NITTA SUSUMU
分类号 G01R31/317;G06F11/22;G06F11/25;G11C29/10 主分类号 G01R31/317
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