Driver circuit

摘要

A circuit comprises a voltage supply node, a reference voltage node, and a plurality of transistors coupled with the voltage supply node and the reference voltage node. The circuit also comprises a circuit input, a first delay element and a second delay element. The first delay element is coupled with the circuit input and one transistor of the plurality of transistors. The second delay element is coupled with the circuit input and a second transistor of the plurality of transistors. The circuit further comprises a circuit output coupled with the first transistor of the plurality of transistors and the second transistor of the plurality of transistors. The circuit additionally comprises a bias generator coupled with the circuit output, the first transistor of the plurality of transistors and the second transistor of the plurality of transistors.

主权项

1. A driver circuit, comprising:
a voltage supply node configured to carry a first voltage; a reference voltage node configured to carry a reference ground voltage; a first transistor having a source, a drain, and a gate, the source of the first transistor is coupled with the voltage supply node; a second transistor having a source, a drain, and a gate, the source of the second transistor is coupled with the drain of the first transistor, and the gate of the second transistor is configured to receive a first bias signal having a second voltage less than the first voltage; a third transistor having a source, a drain, and a gate, the source of the third transistor is coupled with the drain of the second transistor; a fourth transistor having a source, a drain, and a gate, the drain of the fourth transistor is coupled with the drain of the third transistor; a fifth transistor having a source, a drain, and a gate, the drain of the fifth transistor is coupled with the source of the fourth transistor, and the gate of the fifth transistor is configured to receive a second bias signal having a third voltage less than the second voltage; a sixth transistor having a source, a drain, and a gate, the drain of the sixth transistor is coupled with the source of the fifth transistor, and the source of the sixth transistor is coupled with the reference voltage node; a circuit input configured to receive an input signal having a fourth voltage less than or equal to the third voltage; a first delay element coupled with the circuit input and the gate of the first transistor, the first delay element is configured to receive the input signal and to output a first delayed signal having a fifth voltage ranging from the second voltage to the first voltage; a second delay element coupled with the circuit input and the gate of the sixth transistor, the second delay element is configured to receive the input signal and to output a second delayed signal having a sixth voltage less than or equal to the third voltage; a circuit output coupled with the drain of the third transistor and the drain of the fourth transistor; and a bias generator having an input and an output, the input of the bias generator is coupled with the circuit output, and the output of the bias generator is coupled with the gate of the third transistor and the gate of the fourth transistor, wherein the bias generator is configured to output a third delayed signal having a seventh voltage ranging from the third voltage to the second voltage.