发明名称 Method and apparatus for tile based rendering using tile-to-tile locality
摘要 Disclosed is a method and apparatus for performing tile-based rendering. A sequence of tiles to be processed may be determined based on a locality among the tiles. A tile dispatch unit selects a subsequent tile to be dispatched, based on the determined sequence. The tile dispatch unit may check whether an idle fragment processor exists among the plurality of fragment processors, and may dynamically dispatch the selected tile to an idle fragment processor
申请公布号 US9514506(B2) 申请公布日期 2016.12.06
申请号 US201213452095 申请日期 2012.04.20
申请人 Samsung Electronics Co., Ltd. 发明人 Lee Won Jong;Jung Seok Yoon
分类号 G06T1/20;G06F9/50 主分类号 G06T1/20
代理机构 NSIP Law 代理人 NSIP Law
主权项 1. An image processing method of a graphic processing unit (GPU) including a plurality of fragment processors, the method comprising: reading geometrically processed tile data from an external memory disposed outside of the GPU, and connected to the GPU via a system bus; determining a sequence of a plurality of tiles to be processed by at least one of the plurality of fragment processors, based on a locality of each tile among the plurality of tiles; selecting a tile to be processed, based on the determined sequence; checking a plurality of fragment processors inside the GPU, in response to determining any fragment processor being in an idle state, wherein the checking continues in response to a fragment processor being determined not to be in an idle state, and wherein the checking is delayed for a predetermined time before being performed again in response to the fragment processor being determined to be in the idle state; allocating the tile to be processed to an idle fragment processor among the plurality of fragment processors, based on the determined sequence; and rendering, by the fragment processor to which the tile is allocated, the allocated tile, wherein each of the plurality of fragment processors is configured to perform rendering of a tile by using a respective internal cache, and wherein each of the plurality of fragment processors is configured to access, by using a shared cache, data for performing rendering with respect to allocated tiles.
地址 Suwon-si KR