发明名称 MEMORY ERASING CIRCUIT
摘要 <p>PURPOSE:To enhance the secret maintainability of stored data by interrupting immediately the power source of a volatile memory and erasing the stored data, when an attachable/detachable connector is removed. CONSTITUTION:When connectors 3a, 3b are in a coupled state, a capacitor 11 is charged with the voltage of a power source 21, and what is called in the state of a floating power source, the charging voltage VBC of the capacitor 11 is supplied to a pull-up resistance 12 and a changeover switching circuit 13. Subsequently, when the connectors 3a, 3b are detached, a second control line 14 is released from a grounding state, and a second control line 14 is connected to the power source voltage VBC through the pull-up resistance 12 of a high resistance, and also, held in a prescribed H level in a state that it is connected to the changeover switching circuit 13. When a second control line 14 goes to an H level, the changeover switching circuit 13 is switched immediately, and stored data in a memory 4 is brought to breakdown.</p>
申请公布号 JPH02141848(A) 申请公布日期 1990.05.31
申请号 JP19880296640 申请日期 1988.11.22
申请人 NEC CORP 发明人 NAKAMURA KAZUHITO
分类号 G06F12/14;G06F1/00;G06F1/30;G06F21/06 主分类号 G06F12/14
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