发明名称 PROCESSOR RESET SYSTEM
摘要 <p>PURPOSE:To reduce the burden on a program by giving a time-out signal from a timer circuit to a processor to stop the operation at the time of not giving a reset signal from the processor to the timer circuit and eliminating a need of time management of the reset signal by the processor itself. CONSTITUTION:A time management signal (a) having a certain cycle is always generated from a timer circuit 2 and is given to a processor 1. When the processor 1 is normally operated, a reset signal (b) is generated based on the time management signal from the timer circuit 2 and is given to the timer circuit 2; but when the processor 1 runs away because of the occurrence of abnormality, a time-out signal (c) is generated from the timer circuit 2 and is given to the processor 1 because the reset signal is not given from the processor 1 to the timer circuit 2. Thus, the processor 1 stops the operation to stop runaway.</p>
申请公布号 JPH02141836(A) 申请公布日期 1990.05.31
申请号 JP19880296953 申请日期 1988.11.24
申请人 FUJITSU LTD 发明人 KITAMURA KOICHI;YAMAZAKI NAOMI;SUGITA KIYOSHI
分类号 G06F1/24;G06F11/30 主分类号 G06F1/24
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