High speed CMOS bus driver circuits.

摘要

A high speed bus driver circuit is disclosed that minimizes output signal oscillation by maintaining the clamp voltage at specified levels. The driver circuit includes a pair of voltage preference circuits (102,104) that are designed to deliver the appropriate clamp voltages even at the best case speed corners, the circuit prevents simultaneous turn on of drive transistors (MP1,MN1), equalizes the propagation delay and provides for first access for tri-stating the bus driver transistors.