发明名称 |
Automatic layout standard cell routing |
摘要 |
A method of interconnecting transistors and other devices in order to optimize area of a layout of a cell while honoring performance constraints (1502) and enhancing yield starts with a prerouting step (152) that routes adjacent transistors using diffusion wiring (1506), routes power and ground nets (1508), routes aligned gates (1510), routes all remaining aligned source/drain nets as well as any special nets (1512). Next, all of the remaining nets are routed using an area based router (1408). Nets are order based on time criticality or net topology (1602). A routing grid is assigned for all the layers to be used in routing (1604). An initial coarse routing is performed (1606). Wire groups are assigned to routing layers (1608). Routing is improved and vias are minimized (1610). A determination is then made whether the routing solution is acceptable (1612). If the routintg solution is not acceptable, the routing space is expanded and routing costs and via costs are modifyied to improve the routing solution. Finally, the best routing solution is picked (1414).
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申请公布号 |
US5987086(A) |
申请公布日期 |
1999.11.16 |
申请号 |
US19960740721 |
申请日期 |
1996.11.01 |
申请人 |
MOTOROLA INC. |
发明人 |
RAMAN, SRILATA;GURUSWAMY, MOHANKUMAR;DULITZ, DANIEL WESLEY;CHILUVURI, VENKATA K. R.;MAZIASZ, ROBERT L. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
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