Clock signal generator

摘要

The clock signal generator can be used to generate a first and/or a second output clock signal from an input clock signal. The rising and/or falling edges of the input clock signal are shifted using delay stages. The clock signal generator has a delay stage with a plurality of delay elements that are wired up in parallel and that have different delay lengths, and a selection device that is used to determine which of the output signals from the delay elements is to be output as the output signal of the delay stage.