发明名称 COMPUTER SYSTEM GUARANTEEING INSTRUCTION EXECUTION ORDER
摘要 PROBLEM TO BE SOLVED: To provide a computer system capable of improving performance without using an order guarantee instruction for waiting execution until influence that all preceding instructions give terminates. SOLUTION: An LSYNC instruction for suppressing the start of a subsequent instruction until the completion of an operation in the instruction processor of all preceding instructions and an LSYNC stop mechanism 105 are newly provided. When the LSYNC instruction is dispatched, the LSYNC stop mechanism 105 monitors the use states of respective operation units 110, 120 and 130 and suppresses the execution start of the instruction after the LSYNC instruction if at least one and above instructions are in the middle of execution. When all instructions preceding the LSYNC instruction completes in the instruction processor, the completion is detected and the dispatch operation of the instruction after the LSYNC instruction is resumed.
申请公布号 JP2000181712(A) 申请公布日期 2000.06.30
申请号 JP19980360296 申请日期 1998.12.18
申请人 HITACHI LTD 发明人 SUGITA TETSUO;SUKEGAWA NAONOBU;NAKAHATA MASAYA;SAIGAN YUUICHI
分类号 G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/38
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