| 摘要 |
A delay circuit of delay locked loop(DLL) and a controlling method thereof are provided to selectively control single or dual delay lines in order to expand an operating frequency range. A first delay circuit unit(100) delays an input signal(CLK_in) as much time as a first control signal(Sr0~Sr4,Sf0~Sf3) and outputs a first delay signal(CLK_in_dlyU1) and a second delay signal(CLK_in_dlyL1). The first delay circuit unit includes a single delay line(110). A second delay circuit unit(200) delays the first and second delay signal as much time as a second and third control signal(SL0~SL4) and outputs a third delay signal(CLK_in_dlyU2) and a fourth delay signal(CLK_in_dlyL2). The second delay circuit unit includes dual delay lines(210,220). |
