Voltage doubler and nonvolating memory device having the same

摘要

A voltage doubler includes first to fourth transistors, a first capacitor connected between a first node and a first clock terminal configured to receive a first clock signal. A second capacitor is connected between a second node and a second clock terminal configured to receive an inverted first clock signal. A first gate control unit is configured to control the first and second transistors using the first clock signal and the inverted first clock signal, and a second gate control unit is configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal. A load capacitor is connected between the output terminal and a ground terminal.

主权项

1. A voltage doubler comprising:
a first transistor connected between a first node and an input terminal configured to receive an input voltage; a second transistor connected between the input terminal and a second node; a third transistor connected between the first node and an output terminal configured to output an output voltage; a fourth transistor connected between the second node and the output terminal; a first capacitor connected between the first node and a first clock terminal configured to receive a first clock signal; a second capacitor connected between the second node and a second clock terminal configured to receive an inverted first clock signal; a first gate control unit configured to control the first and second transistors using the first clock signal and the inverted first clock signal; a second gate control unit configured to control the third and fourth transistors using a second clock signal and an inverted second clock signal; and a load capacitor connected between the output terminal and a ground terminal.