发明名称 Capacitive load PLL with calibration loop
摘要 A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
申请公布号 US9391626(B2) 申请公布日期 2016.07.12
申请号 US201414456064 申请日期 2014.08.11
申请人 Taiwan Semiconductor Manufacturing Co., Ltd. 发明人 Chern Chan-Hong;Chung Tao Wen;Huang Ming-Chieh;Lin Chih-Chang;Huang Tsung-Ching;Hsueh Fu-Lung
分类号 H03L7/06;H03L7/10;H03L7/099;H03L7/18;H03L7/097;H03L7/107 主分类号 H03L7/06
代理机构 Duane Morris LLP 代理人 Duane Morris LLP
主权项 1. A circuit, comprising: a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal; a tuning circuit coupled to the voltage controlled oscillator for outputting a first control signal in response to a voltage of the first input signal and for performing a first adjustment of a frequency of the oscillating output signal; and a calibration circuit coupled to the voltage controlled oscillator, the calibration circuit including a state machine configured to output a second control signal to the capacitive-load voltage controlled oscillator for performing a second adjustment of the frequency of the oscillating output signal, wherein the calibration circuit is configured to receive an input voltage and output the second control signal in response to a comparison of the input voltage to at least one reference voltage; wherein the voltage controlled oscillator comprises a plurality of inverters coupled in series with one another, each of the plurality of inverters having a respective output coupled to a first capacitor and a second capacitor, the first and second capacitors being disposed in parallel with one another and independently coupled to the output of the respective inverters through first and second switches, respectively, wherein the first switch is controlled by the first control signal and the second switch is controlled by the second control signal.
地址 Hsin-Chu TW