发明名称 Hierarchical write-combining cache coherence
摘要 A method, computer program product, and system is described that enforces a release consistency with special accesses sequentially consistent (RCsc) memory model and executes release synchronization instructions such as a StRel event without tracking an outstanding store event through a memory hierarchy, while efficiently using bandwidth resources. What is also described is the decoupling of a store event from an ordering of the store event with respect to a RCsc memory model. The description also includes a set of hierarchical read-only cache and write-only combining buffers that coalesce stores from different parts of the system. In addition, a pool component maintains partial order of received store events and release synchronization events to avoid content addressable memory (CAM) structures, full cache flushes, as well as direct write-throughs to memory. The approach improves the performance of both global and local synchronization events and reduces overhead in maintaining write-only combining buffers.
申请公布号 US9396112(B2) 申请公布日期 2016.07.19
申请号 US201314010096 申请日期 2013.08.26
申请人 Advanced Micro Devices, Inc. 发明人 Hechtman Blake A.;Beckmann Bradford M.
分类号 G06F12/08 主分类号 G06F12/08
代理机构 Volpe and Koenig, P.C. 代理人 Volpe and Koenig, P.C.
主权项 1. A method comprising: receiving a memory event; when the memory event is a store event, the method further comprises: writing a first data to a write-only, level n cache, where n is an integer representing a level of cache hierarchy;writing, to a level n pool, a store entry that includes an address of the first data written in the level n cache, wherein the level n pool stores store entry, a plurality of a prior received store entries, and a release marker entry, and the stored release marker entry maintains a partial release order among the store entry and the plurality of prior received store entries by dividing them into groups within the pool such that all store entries positioned before the release marker entry are to be released before all store entries positioned after the release marker entry, wherein no particular order of store entries within the particular groups exists; andwhen a release marker is present, ordering the store entry in the level n pool to follow a most-recent release marker; and when the memory event is a load event, the method further comprises: searching a read-only, level n cache for a second data;determining whether the second data is present in a corresponding write-only, level n cache;when the second data is found in the read-only, level n cache and the second data is not found in the corresponding write-only, level n cache, reading the second data from the read-only, level n cache; andwhen the second data is found in the corresponding write-only, level n cache, reading the second data from the write-only, level n cache.
地址 Sunnyvale CA US