SCREENING FOR DATA RETENTION LOSS IN FERROELECTRIC MEMORIES

摘要

Described examples include a data retention reliability screen (45) of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels (54), after programming to a high polarization capacitance data state (48) and a relaxation time (50) at an elevated temperature (52). Fail bit counts of the sample groups at the various reference voltage levels (54) are used to derive a test reference voltage (58), against which all of the FRAM cells in the integrated circuit are then tested (64) after preconditioning (60) and another relaxation interval (62) at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure (65).