Circuit arrangement for logic built-in self-test of a semiconductor device and a method of operating such circuit arrangement

摘要

A circuit arrangement for Logic Built-In Self-Test (LBIST) includes a clock source configured to generate a system clock, a first clock division circuitry configured to derive a first punched-out clock and a plurality of scan chains operable at the first punched-out clock. Each scan chain has an associated output circuitry responsive to a leading edge of the first punched-out clock. The circuit arrangement includes a second clock division circuitry configured to derive a second punched-out clock. The second punched-out clock has a delay of one or more system clock periods relative to the first punched-out clock. A compacting logic is configured to compact signals received from the scan chains. A sequential retiming element connects the compacting logic to an input circuitry of a MISR. The sequential retiming element is responsive to a trailing edge of the second punched-out clock. The input circuitry is responsive to a leading edge of the second punched-out clock.

主权项

1. A circuit arrangement for Logic Built-In Self-Test (LBIST) of a semiconductor device, the circuit arrangement comprising:
a clock source configured to generate a system clock having a system clock pulse duration and a system clock period; a first clock division circuitry configured to derive a first punched-out clock from the system clock by periodically suppressing one or more successive clock pulses of the system clock to obtain the first punched-out clock having a pulse duration corresponding to the system clock pulse duration and a cycle time corresponding to a plurality of system clock periods; a plurality of scan chains operable at the first punched-out clock, each scan chain having an associated output circuitry responsive to a leading edge of the first punched-out clock; a second clock division circuitry configured to derive a second punched-out clock from the system clock by periodically suppressing one or more successive clock pulses of the system clock to obtain the second punched-out clock with a pulse duration corresponding to the system clock pulse duration and a cycle time corresponding to the cycle time of the first punched-out clock, the second punched-out clock having a delay of one or more system clock periods relative to the first punched-out clock; a signature generation circuitry comprising a compacting logic, a sequential retiming element and a Multi-Input Signature Register; the Multi-Input Signature Register being operable at the second punched-out clock, the Multi-Input Signature Register having an input circuitry responsive to a leading edge of the second punched-out clock; the compacting logic having a plurality of compactor inputs connected to the output circuitries of the plurality of scan chains and a compactor output, and configured to compact signals provided to its inputs into a compacted output on its output; the sequential retiming element being connected with a data input to the output of the compacting logic and connected with a data output to the input circuitry of the Multi-Input Signature Register; the sequential retiming element being operable at the second punched-out clock, the data input of the sequential retiming element being responsive to a trailing edge of the second punched-out clock.