| 主权项 |
1. A tristate gate, comprising:
an output port; an n-type transistor and a p-type transistor, each of the n-type transistor and the p-type transistor having at least a first gate and a second gate, each of the n-type transistor and the p-type transistor having a drain electrode connected to the output port, the second gate of the n-type transistor connected to a first output enable terminal and the second gate of the p-type transistor connected to a second output enable terminal different from the first output enable terminal, the n-type transistor and the p-type transistor configured such that a high-impedance value (Z) on the output port is set by controlling threshold voltages of the n-type transistor and the p-type transistor via their respective second gates, wherein the threshold voltages of the n-type transistor and the p-type transistor are controlled independently of each other; an input port connected to the first gate of the n-type transistor; and a control port connected to the first gate of the p-type transistor, wherein the control port is different from the input port and is configured to enable or disable a signal path from the input port to the output port. |
