发明名称 |
System and method for computer memory with linked paths |
摘要 |
A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer. |
申请公布号 |
US9501432(B2) |
申请公布日期 |
2016.11.22 |
申请号 |
US201414246643 |
申请日期 |
2014.04.07 |
申请人 |
International Business Machines Corporation |
发明人 |
Cordero Edgar R.;Paulraj Girisankar;Chinnakkonda Vidyapoornachary Diyanesh B. |
分类号 |
G06F13/28;G06F13/16;G06F12/02;G06F3/06 |
主分类号 |
G06F13/28 |
代理机构 |
|
代理人 |
Dobson Scott S. |
主权项 |
1. A method for memory mirroring, the method comprising:
disabling a first connection between a first memory buffer and a first memory controller, the first memory buffer having a first high speed memory channel and a second high speed memory channel, the first connection connected to the first memory buffer through the first high speed memory channel; enabling a second connection between a second memory buffer and the first memory buffer, the second memory buffer having a third high speed memory channel and a fourth high speed memory channel, the second connection connecting the second high speed memory channel and the third high speed memory channel, the first memory buffer connected to a first memory module set, the second memory buffer connected to a second memory module set; communicating a write command from a second memory controller to the second memory buffer, the second memory controller connected to the second memory buffer through the fourth high speed memory channel; communicating the write command from the second memory buffer to the first memory buffer; and communicating the write command from the first memory buffer to the first memory module set. |
地址 |
Armonk NY US |