发明名称 Mounting method
摘要 A mounting method of mounting chips on a substrate includes a temporarily-bonding process, and a main-bonding process. Temporarily-bonding process is to perform a first basic process, repeatedly depending on the number of the chips. First basic process includes a first step and a second step. First step is to align, on a first metal layer of the substrate, a second metal layer of each chip. Second step is to temporarily bond each chip by subjecting the first and second metal layers to solid phase diffusion bonding. Main-bonding process is to perform a second basic process, repeatedly depending on the number of the chips. Second basic process includes a third step and a fourth step. Third step is to recognize a position of each chip temporarily mounted on the substrate. Fourth step is to firmly bond each chip by subjecting the first and second metal layers to liquid phase diffusion bonding.
申请公布号 US9508679(B2) 申请公布日期 2016.11.29
申请号 US201314420181 申请日期 2013.03.11
申请人 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. 发明人 Ueda Mitsuhiko;Sanagawa Yoshiharu;Aketa Takanori;Hayashi Shintaro
分类号 H01L23/00;B23K20/00;H01L21/52;H01L21/683 主分类号 H01L23/00
代理机构 Greenblum & Bernstein, P.L.C. 代理人 Greenblum & Bernstein, P.L.C.
主权项 1. A mounting method of mounting chips on a substrate, comprising: a temporarily-bonding process of temporarily individually bonding the chips on the substrate; and a main-bonding process of firmly individually bonding, on the substrate, the chips temporarily bonded on the substrate, the temporarily-bonding process being of performing a first basic process, repeatedly depending on a number of the chips to be mounted on the substrate, the first basic process comprising: aligning, on a first metal layer of the substrate, a second metal layer of each chip; and temporarily bonding each chip on the substrate by applying pressure from a side of each chip, in a state where a planar bonding surface of the second metal layer is brought into contact with a planar bonding surface of the first metal layer, after the alignment to subject the first and second metal layers to solid phase diffusion bonding, wherein the solid phase diffusion bonding is ultrasonic bonding or surface activation bonding, the main-bonding process being of performing a second basic process, repeatedly depending on the number of the chips on the substrate, the second basic process comprising: recognizing a position of each chip temporarily mounted on the substrate; and firmly bonding each chip on the substrate by applying pressure from the side of each chip after the recognition to subject the first and second metal layers to liquid phase diffusion bonding.
地址 Osaka JP