Transmission of data in bus system - using integrated circuit synchronous demodulator comprising time delay shift register and filter

摘要

A demodulator is provided for a phase shift keyed (PSK) or freq. shift keyed (FSK) modulated siganl, in a bus system. The received siganl (S(E)) is delayed by time (TD) in a delay circuit (6) and recombined with the original signal (S(E)). The time delay (TD) is a half period of the bit rate freq.. Pref. the demodulated signal (S(E)) is filtered by a correlation filter (7,8) to produce a signal (y') which is the compared by comparitor (9) with a threshold value to produce a digital signal (Y''). USE/ADVANTAGE - UART (Universal Asynchronous Receiver Transmitter); allows use of digital circuitry.