| 摘要 |
A high performance variable length decoder which includes a tagging circuit that tags boundaries of code words in an incoming bit stream, providing a tag stream output and a bussed bit stream output that coincides in time with the tag stream output. The bussed tag stream output is connected to an input of a high speed parallel word length computation circuit, and the bussed bit stream output is connected to an input of a parallel value decoder circuit. The parallel word length computation circuit (word length decoding loop) receives the bussed tag stream and computes (decodes) the length of a singular code word in a singular mode of operation, or the lengths of one or more contiguous code words in a contiguous mode of operation. The word length computation circuit uses faster type independent look-up tables for decoding the lengths of the code words represented by the bussed tag stream, thereby enabling much faster word length decoding for the overwhelming majority of code words in the incoming bit stream. The word type independent decoding operation increases the degree of parallelism in processing, and therefore the throughput of the variable length decoder that can be achieved at lower clock rates. The parallel value decoder circuit receives the bussed bit stream from the tagging circuit and decodes the values of a singular code word in a first or singular mode of operation, or one or more contiguous code words in parallel in a second or contiguous mode of operation. The mode of operation (either singular or contiguous) is selected in accordance with a control signal generated by a control circuit which controls the operation of the variable length decoder on the basis of current and previously decoded code words, in accordance with a prescribed decoding protocol, e.g. an MPEG protocol. |
