发明名称 Planar view TEM sample preparation from circuit layer structures
摘要 A method of preparing a planar view TEM sample of a planar portion of a circuit layer structure formed on a substrate. The method includes polishing the substrate circuit layer structure until a cross-sectional polishing face has substantially reached a first side face of the planar portion of the circuit layer structure; forming a trench structure in the cross-sectional polishing face. The trench structure extends into the cross-sectional polishing face substantially in the direction parallel to the substrate such that top and bottom faces of the planar portion of the circuit layer structure are exposed, wherein the planar portion of the circuit layer structure extends substantially parallel to the substrate from the first side face. The method further includes performing a cut around the first side face to free the planar portion of the circuit layer structure.
申请公布号 US7208965(B2) 申请公布日期 2007.04.24
申请号 US20040022325 申请日期 2004.12.23
申请人 SYSTEMS ON SILICON MANUFACTURING CO. PTE. LTD. 发明人 ZHANG WEN YI;OH SIEW KHIM
分类号 G01R31/02 主分类号 G01R31/02
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