Circuits and methods for performance optimization of SRAM memory

摘要

In aspects of the present application, circuitry for storing data is provided including a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, and one or more precharge circuits in the SRAM memory circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal. The precharge control signal within the SRAM circuit is operable to cause coupling transistors within the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage responsive to mode signals output from a memory controller circuit external to the SRAM circuit, indicating a bitline precharge is to be performed.

主权项

1. A circuit for data storage, comprising:
a static random access memory (SRAM) circuit operable to store data in an array of SRAM cell circuits arranged in rows and columns, each SRAM cell circuit coupled to one of a plurality of word lines disposed along the rows of SRAM cell circuits, and each SRAM cell coupled to a pair of complementary bit lines disposed along the columns of SRAM cells circuits, the SRAM cell circuits each operable to output a differential voltage corresponding to a stored datum on the corresponding pair of complementary bit lines responsive to a row select voltage on the word line coupled to the SRAM cell circuit, and one or more precharge circuits in the SRAM circuit coupled to one or more pairs of the complementary bit lines and operable to charge the pairs of complementary bit lines to a precharge voltage, responsive to a precharge control signal; and a memory controller circuit external to and coupled to the SRAM circuit and operable to control read and write data accesses to the SRAM circuit by outputting one or more precharge control signals to the SRAM circuit; wherein the precharge control signal within the SRAM circuit is operable to cause coupling transistors within the precharge circuits of the SRAM circuit to couple a pair of complementary bit lines to the precharge voltage, responsive to the precharge control signals output from external memory controller circuit indicating a bitline precharge is to be performed; wherein the memory controller circuit further comprises precharge mode control circuitry operable to output: a burst mode enable signal to the SRAM circuit indicating that a next memory address to be accessed is to a memory cell along the same row as the current row corresponding to the current address input to the SRAM circuit; a precharge first mode signal to the SRAM circuit when a sequence of SRAM memory accesses will occur along the same row of SRAM cells; and a precharge last mode signal to the SRAM circuit when a sequence of SRAM memory accesses will occur that requires access to a row of SRAM cells that differs from the row of SRAM cells that is currently being accessed.