发明名称 Threshold voltage expansion
摘要 Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.
申请公布号 US9384801(B2) 申请公布日期 2016.07.05
申请号 US201414461154 申请日期 2014.08.15
申请人 INTEL CORPORATION 发明人 Pandey Abhinav;Belgal Hanmant P.;Damle Prashant S.;Kripanidhi Arjun;Uribe Sebastian T.;Ly-Gagnon Dany-Sebastien;Rangan Sanjay;Pangal Kiran
分类号 G11C7/00;G11C7/12;G11C29/50;G06F11/10;G11C14/00;G11C7/04;G11C13/00 主分类号 G11C7/00
代理机构 Schwabe Williamson & Wyatt PC 代理人 Schwabe Williamson & Wyatt PC
主权项 1. An apparatus comprising: a plurality of memory cells, wherein individual memory cells of the plurality of memory cells are configured to store one or more bits of data; and a bias logic coupled with the individual memory cells, the bias logic to: apply a dummy-read voltage to the plurality of memory cells, to return the plurality of memory cells that are in a set state to a voltage pre-drift state;apply, subsequent to application of the dummy-read voltage, a read voltage to the plurality of memory cells;apply a voltage bias pulse to a subset of the plurality of memory cells in a reset state, as a result of the application of the read voltage, to accelerate a voltage drift of the memory cells in the reset state.
地址 Santa Clara CA US