发明名称 トレンチゲート型MOS半導体装置のトレンチ平均深さおよびスイッチング特性の評価方法および半導体チップの選別方法
摘要 PROBLEM TO BE SOLVED: To provide a method of evaluating a trench average depth of a trench gate type MOS semiconductor device capable of evaluating and selecting a trench average depth and switching characteristics of a semiconductor chip in a wafer state by non-destruction and by a simple test circuit without using a high-voltage power supply, with respect to a wafer that undergoes a wafer process of the trench gate type MOS semiconductor device.SOLUTION: After termination of a step of burying a gate electrode 8 via a gate insulating film 7 in a trench 11 provided on a surface side of a semiconductor wafer 21 and a step of forming metal main electrodes 5 and 6 on both principal surfaces, a rectangular pulse voltage is applied from a predetermined negative voltage value to a predetermined positive voltage value, between the gate electrode 8 in a semiconductor chip 10 formed in the semiconductor wafer 21 and the rear face metal electrode 5 to measure a gate charging time A when a voltage reaches the predetermined positive voltage value. A trench average depth of the semiconductor chip 10 corresponding to the measured gate charging time A is calculated from a calibration curve indicating a relation between a known trench average depth and a gate charging time.
申请公布号 JP6007507(B2) 申请公布日期 2016.10.12
申请号 JP20120032809 申请日期 2012.02.17
申请人 富士電機株式会社 发明人 小澤 毅;小山 幸男
分类号 H01L21/336;H01L21/66;H01L29/739;H01L29/78 主分类号 H01L21/336
代理机构 代理人
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