发明名称 Memory controller, memory system, and memory control method
摘要 According to one embodiment, a memory controller includes a writing destination management unit which determines a writing destination of user data, an encoding unit which generates a parity of the user data, and an ECC management unit which measures a fatigue degree of each certain memory area of a nonvolatile memory, selects an encoding method to instruct the encoding unit to be performed according to the encoding method, and changes the encoding method to an encoding method having a high error correction capability in a case where the fatigue degree corresponding to the writing destination is equal to or higher than a threshold and a total sum of parities is equal to or less than a predetermined amount.
申请公布号 US9520901(B2) 申请公布日期 2016.12.13
申请号 US201414446463 申请日期 2014.07.30
申请人 Kabushiki Kaisha Toshiba 发明人 Suzuki Riki;Hida Toshikatsu;Torii Osamu;Yao Hiroshi;Iwasaki Kiyotaka
分类号 H03M13/00;H03M13/29;G06F11/10;G11C7/10;G11B20/18;G11C29/04 主分类号 H03M13/00
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A memory controller that controls a nonvolatile memory, the nonvolatile memory including a plurality of memory areas, comprising: a writing destination management circuit configured to determine a writing destination of user data in the nonvolatile memory; an encoding circuit configured to encode the user data to generate a parity, the encoding circuit performing the encoding according to a plurality of encoding methods having different error correction capabilities, the plurality of encoding methods including a first encoding method and a second encoding method of which the error correction capability is higher than that of the first encoding method; a decoding circuit configured to decode the user data and the parity which are read out of the nonvolatile memory, the decoding circuit detecting a number of errors in the user data; a writing control circuit configured to control the nonvolatile memory to write the user data at the writing destination determined by the writing destination management circuit; and an Error Correcting Code (ECC) management circuit configured to obtain the number of errors in the user data of each of the plurality of memory areas, to select an encoding method among the plurality of encoding methods to be performed on user data which is stored in a first memory area among the plurality of memory areas, and to instruct the encoding circuit to encode the user data according to the encoding method corresponding to the first memory area, the first memory area corresponding to the writing destination of the user data, wherein the ECC management circuit changes the encoding method corresponding to the first memory area from the first encoding method to the second encoding method when the number of errors in the user data of the first memory area is equal to or higher than a threshold and a total sum of parities of the nonvolatile memory is equal to or less than a predetermined amount, wherein a predetermined size of parity is generated for a first size of the user data when the encoding is performed according to the first encoding method, and the predetermined size of the parity is generated for a second size of the user data smaller than the first size when the encoding is performed according to the second encoding method.
地址 Minato-ku JP